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ACE9020
Receiver and Transmitter Interface
DS4287
ISSUE 5.0
December 1997
ACE9020 is a VHF oscillator, up-converter and prescaler. It is used in an offset modulated transmit architecture where a UHF synthesiser makes the channel selection and a second synthesiser generates a fixed transmit offset. A VCO signal drives a buffer in ACE9020 to feed an onchip prescaler and transmit up-converter. The prescaler is a dual two-modulus divider and drives the main synthesiser input of the ACE9030. The SSB up-converter suppresses the unwanted transmit sideband. The VHF oscillator is buffered to drive the auxiliary synthesiser input of the ACE9030 and is locked to the offset frequency. This frequency is modulated by varying the resonant frequency of the external tank circuit. Both this oscillator and the UHF VCO drive the up-converting mixer to generate the transmit signal. Various power saving modes for battery economy are included. These allow the transmit sections to be shut down during stand-by and the whole chip can be shut down during sleep mode. The circuit techniques used have been chosen to minimise external components and at the same time give very high performance.
Ordering Information
SSOP 28 lead package, code NP28 ACE9020B/KG/NP1S - anti-static sticks ACE9020B/KG/NP1T - tape mounted
PD1 PD2 GND BIAS_REF VCC_TX TXPA+ TXPARSET_TXPA GND_TXOSC TANK+ TANKVCC_DIV GND_OSC MOD_CNTRL
1
28
VCC n.c. n.c. VCC_RX n.c. RXVCOIN GND_RX VCC_TXOSC TXOSCTXOSC+ GND_DIV RATIO_SEL DIV_OUTDIV_OUT+
ACE9020
14 15
Features * Low Power Low Voltage (3.6 to 5.0 V) Operation * Power Down Modes * Differential Signals to Minimise Cross-talk * Auxiliary Oscillator with Transmit Up-converter * Prescaler for Main Synthesiser * Part of the ACE Integrated Cellular Phone Chipset * Small Outline 28 pin Package Applications * AMPS and TACS Cellular Telephone * Two-Way Radio Systems Related Products ACE9020 is part of the following chipset: * ACE9030 Radio Interface and Twin Synthesiser * ACE9040 Audio Processor * ACE9050 System Controller and Data Modem ABSOLUTE MAXIMUM RATINGS
Supply voltage Storage temperature Operating temperature Voltage at any pin Static Sensitivity (HBM) min 6V - 65C to + 150C - 30C to + 85C -0.3V to VCC +0.3V 500V
Note: Pin 1 is identified by moulded spot and by coding orientation.
NP28
Figure 1 - Pin connections - top view
TXOSC+ TXOSCRSET_TXPA TANK+ TANKVHF OSC TXPA+ TXPA-
BIAS_REF PD1 PD2
BIAS & POWER DOWN CONTROL
RXVCOIN
RATIO_SEL DIV_OUT+ DIV_OUT-
MOD_CNTRL
DIVIDE BY 64/65 OR 128/129
Figure 2 - ACE9020 simplified block digram
ACE9020
PIN Connections
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name PD1 PD2 GND BIAS_REF VCC_TX TXPA+ TXPARSET_TXPA GND_TXOSC TANK+ TANKVCC_DIV GND_OSC MOD_CNTRL DIV_OUT+ DIV_OUTRATIO_SEL GND_DIV TXOSC+ TXOSCVCC_TXOSC GND_RX RXVCOIN n.c. VCC_RX n.c. n.c. VCC Type I I Supply I Supply O O I Supply I I Supply Supply I O O I Supply O O Supply Supply I Supply Supply Description Power down control input 1 Power down control input 2 Ground Reference current for bias control Transmit section supply voltage Transmit up-converter open collector output Transmit up-converter open collector output Reference current for transmit oscillator Ground Transmit oscillator tank circuit Transmit oscillator tank circuit Divider section supply voltage Ground Modulus control input Divider output positive Divider output negative Ratio select Ground divider section Transmit oscillator monitor output positive Transmit oscillator monitor output negative Transmit oscillator supply voltage Ground Input buffer for 1GHz VCO signal from ACE9010 No connection Receiver section supply voltage No connection No connection ON/OFF logic supply voltage
Electrical Characteristics
These characteristics apply over these ranges of conditions (unless otherwise stated): TAMB = - 30C to + 85C, VCC = 3.75 0.15V or 4.85 0.15V (see fig. 3 for test circuit).
DC Characteristics
Characteristic Supply Currents Sleep PD1 = 0, PD2 = 0 Standby PD1 = 1, PD2 = 0 Transmit Set Up PD1 = 0, PD2 = 1 Duplex PD1 = 1, PD2 = 1 Input Levels PD1, PD2 High PD1, PD2 Low Mod Cntrl High Mod Cntrl Low Ratio Sel High Ratio Sel Low Input Currents PD1, PD2 High PD1, PD2 Low Min Typ Max 0.11 8 51 63 3.1 0.5 Vcc Vcc/2 - 0.3 Vcc 0.4Vcc 40 0.1 Unit mA mA mA mA V V V V V V A A
6 36 48 1.9 0 Vcc/2 + 0.3 0 0.6Vcc 0
-0.1
2
ACE9020
Electrical Characteristics
These characteristics apply over these ranges of conditions (unless otherwise stated): TAMB = -30C to + 85C, VCC = 3.75 0.15V or VCC 4.85 0.15V (see fig. 3 for test circuit).
AC Characteristics
Characteristic TXOSC Output Differential Output TxOsc Frequency Frequency / Supply Sensitivity Spurii > 700MHz Differential Output Capacitance External Tank Inductance f = 90MHz External Tank Inductance f = 122.5MHz Power up time (from standby) TXPA Output Signal Output Power (RL = 50) Noise at f = +/- 45 MHz Noise at f = +/- 25 kHz Harmonic Content Spurious - Image Spurious (fVCO 2faux) Spurious (fVCO 3faux) Spurious (f = 45MHz 15 kHz) except 2fVCO - 9faux Spurious 2fVCO - 9faux Spurii within 800 to 940 MHz (note1) Other Spurii except image Isolation TXPA off (PD2 = PD1 = 1) Power up time Isolation TXPA to RVCOIN Residual Modulation (note 2) RVCOIN Input Signal Signal Level Input Impedance Divider input frequency Upconverter input frequency Phase Noise f = 45MHz Phase Noise f = 25kHz Spurious - harmonic Spurious - non-harmonic Divider Differential Output Level Output Rise / Fall time Mod Control Set up time Mod Control Hold time Min 500 70 Typ Max Unit mV p-p MHz kHz dBc pF nH nH s dBm dBc/Hz dBc/Hz dBc dBc dBc dBc dBc dBc dBc dBc dB s dB dB dBm MHz MHz dBc/Hz dBc/Hz dBc dBc mV p-p ns ns ns
140 75 -40 2 100 68 65
82 56
0
3
6 -145 -100 -20 -10 -30 -25 -105 -60 -70 -30 25
55 45 -40 -10 50 800 910 1100 1040 -155 -117 -20 -80 600 15 20 1
500
Notes: 1. Exceptions. Harmonics of divider output -37dBc max applicable when fVCO = 975.1354 MHz Ratio = 65 10th Harmonic of faux -47dBc applicable when faux = 90MHz, fVCO = 989.9375MHz 2. Residual modulation referenced to a 1kHz signal giving 3kHz deviation. Measured with 750s de-emphasis and CCITT filter.
2
ACE9020
Vcc
6k8
100p 10
5,12,21,25,28 19 20 11 100n 18p
VCO Control
BB545
TXOsc
+ Vcc
27n 1p
6k8
100p
6
Rxvcoin Mod Cntrl Ratio Sel PD1 PD2
ACE9020
23 7 14 15 16 17 12 4 8 3,9,13, 18,22
+ TXPA -
27p 18n 27n 1p
Tx Output
Div Out
+ -
22k
18k
faux = 90 MHz
Figure 3 - ACE9020 Test circuit
Description
The ACE9020 is designed for use in a transceiver such as an analog cellular phone, which uses an offset modulation transmit architecture. The circuit consists of a VHF voltage controlled oscillator to generate the offset frequency, an upconverter to transmit frequency and also a prescaler for the main UHF phase locked loop. The Rxvcoin signal to the ACE9020 is normally the UHF local oscillator used for downconversion. A basic block diagram is shown in fig. 2, further information on external connections is provided in the test circuit (fig. 3) and the applications diagram (fig. 4). VHF Oscillator This oscillator is a differential design which uses an external tank circuit as shown in fig. 3 and fig. 4. The components shown in fig. 3 give a VCO frequency of 90MHz. A varactor diode is coupled capacitively to the tank circuit; the anode is referenced to ground via a resistor. The VCO control from a synthesiser (eg ACE9030) charge pump output is applied to the cathode of the varactor also through a resistor. These resistors should be the same value to keep the differential circuit balanced. The VCO gain with the components shown will be typically 2 MHz/V. Modulation is applied to the anode via a resistive divider as shown in fig. 4; the actual signal applied to the varactor will be small as the frequency deviation will typically be a maximum of 12kHz in many applications. Differential buffered outputs from the oscillator (TXOSC) interface directly to the ACE9030 auxiliary synthesier inputs. Upconverter An image reject mixer is used for the upconversion. This provides typically 20dB rejection of the unwanted upper sideband. The quadrature networks for the mixer are all provided on chip; this is optimised for UHF local oscillator and VHF offset oscillator frequencies typically used for analog cellular phones on the AMPS and TACS systems. Further filtering of the TXPA output will be required to provide further suppression of the unwanted upper sideband, local oscillator signal and harmonics to meet cellular telephone specifications. SAW filters are available for the various transmit frequency bands. The upconverter outputs (TXPA + and -) are differential current outputs. The use of differential outputs minimises current switching within the device and thus minimise crosstalk to other circuit blocks. The TXPA outputs must be matched to the external filter, normally 50 and single-ended. The network shown in fig. 3 provides a transformation from 400 differential to 50 single-ended and also provides dc bias from the Vcc supply to the open collector TXPA outputs. This network provides plus and minus 90 phase shift in each output which are then summed. Alternatively a Balun transformer could be used, it will again be necessary to provide dc bias to the TXPA outputs. The load to the current outputs should be maximised to obtain the maximum power output; 400 is an optimum figure as higher values require impractical component values for matching. Prescaler The two modulus prescaler is part of the UHF phase locked loop. It will typically be operating with ACE9030 radio interface and synthesiser. There is also a choice of divider ratio, set by the ratio select input as shown in table. 1, below. Ratio Sel = LOW /129 /128 Table 1 The differential divider outputs can be directly coupled to the ACE9030 main synthesiser inputs. Ratio Sel = HIGH /65 /64
Mod_Cntrl = LOW Mod_Cntrl = HIGH
4
ACE9020
Power Control Circuits The inputs PD1 and PD2 are used to select the operating modes as shown below:
PD1 0 1 1 0 PD2 0 0 1 1 Mode Sleep Standby Transmit Set Up Duplex All circuits off Prescaler On Prescaler, VHF oscillator on. Upconverter off All circuits on
determined primarily by the VHF PLL settling time. The power down inputs can then be set to (0, 1) the full duplex condition. The intermediate state should also be used during a `handoff' during conversation on an analogue cellular phone, the VHF PLL continuing to operate while the main UHF PLL changes channel, the transmit output being disabled. It is also recommended that the intermediate state is used when going from duplex (0, 1) to standby (1, 0) modes. Operating Notes Good RF layout techniques should be used for this device to obtain optimum performance and also minimise crosstalk between circuit blocks. RF supply decoupling should be provided adjacent to Vcc pins; a value of 27pF is recommended. Two external bias resistors are required. A 22k resistor is connected from BIAS REF (Pin 4) to ground. This sets an accurate reference current for the chip. An 18k resistor is connected from RSET TXPA (Pin 8) to ground which controls the output level of the VHF oscillator and hence the TXPA output level.
The power down inputs (PD1, PD2) are compatible with ACE9030 digital outputs (DO5, 6, 7). These modes allow circuit operation and power consumption to be optimised. The ACE9020 can be put in sleep mode (0, 0) when the power consumption is minimal. The standby mode (1, 0) is used when the phone is in standby (receive only). The prescaler is operational to maintain the main UHF PLL; all circuitry associated with transmit functions is turned off. There is an intermediate transmit set up state (1, 1). This allows the VHF oscillator and phase locked loop to stabilise before enabling the upconverter, preventing spurious transmissions. The time required for this state will be
Figure 4 - Application Diagram
4
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